• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention provides for a method of manufacturing a simplified high Q inductor substrate and a semiconductor device having that substrate. The method for manufacturing the simplified high Q inductor substrate preferably comprising forming a base substrate over a semiconductor wafer, wherein the base substrate has a given dopant concentration and then forming an epitaxial (EPI) layer over the base substrate. The EPI layer includes epitaxially forming a first doped region in the EPI layer over the base substrate and then epitaxially forming a second doped region in the EPI layer over the first doped region. The first doped region has a dopant concentration greater than the given dopant concentration of the base substrate, and the second doped region has a dopant concentration less than the first doped region.
    公开号:US20010009795A1
    申请号:US09/800,049
    申请日:2001-03-05
    公开日:2001-07-26
    发明作者:Jerome Chu；John LaBarre；Wen Lin；Blair Miller
    申请人:Agere Systems Guardian Corp；
    IPC主号:H01L28-10
    专利说明:
    [0001] The present invention is directed, in general, to semiconductor devices and, more specifically, to a semiconductor device having a simplified high Q inductor substrate and a method for manufacturing that substrate. [0001] BACKGROUND OF THE INVENTION
    [0002] Integrated circuits are critical to the success of many technology areas, and especially critical to the continued growth of the telecommunications industry. Semiconductor devices in the form of integrated circuits are the cornerstone of many telecommunications systems involving a broad spectrum of different circuits, many of which require high frequency capabilities. High frequency telecommunications circuits typically require the use of inductors to either tune a circuit to a particular desired frequency, to perform critical circuit functions such as maintaining a critical current flow, or to filter and eliminate undesired electrical noise from desired signals. [0002]
    [0003] If a collection of inductors is needed to allow a particular integrated circuit device to perform correctly, the use of discrete inductors that are separate from the integrated circuit device may give rise to implementation problems due to the need for many interconnections. This situation has driven the industry to move in the direction of integrating as many of these needed inductors as possible into the semiconductor device itself. However, the integration of an inductor into a semiconductor device creates other problems due to the inductor's magnetic nature. [0003]
    [0004] The magnetic field associated with a conductive coil forming an inductor is a well known donut or torus shaped structure, usually having an elliptical cross-section. This magnetic field alternates with the frequency applied to the inductor and may cause interfering effects within the semiconductor device itself. The generation of spurious currents due to this magnetic field may produce several undesirable effects. One of these is to reduce the effectiveness of the conductive coil's ability to perform as an inductor due to energy losses. [0004]
    [0005] It is well known that the Q of an inductive circuit is a figure of merit that relates the energy stored to the energy dissipated or lost. High Q inductor circuits (a Q of [0005] 10 or greater) conserve sufficient energy to allow an appropriate inductive response. Alternately, low Q inductor circuits (a Q of three or less) lose a sufficient portion of the energy applied, often through the generation of eddy currents in the semiconductor device, causing them to perform poorly as inductive elements. Eddy currents are minimized in a semiconductor layer that corresponds to lower dopant concentrations thereby providing a layer having comparatively higher resistivity.
    [0006] An example of an integrated circuit, that will not support a high Q inductor, has a highly conductive substrate and a highly resistive epitaxial (EPI) layer grown on the substrate. This integrated circuit is typical of a fundamental building block used in many current communications microchips. This substrate may have a positive dopant, such as boron, with a P+ dopant concentration that is typically greater than 10[0006] 8 cm−3 making the substrate highly conductive electrically. The EPI layer also has a positive dopant but with a reduced or P− dopant concentration of about 1015 cm−3 making the EPI layer highly resistive.
    [0007] The highly conductive substrate is used to prevent a functionally destructive phenomenon known as latch-up. Latch-up occurs when a voltage is applied to a semiconductor device in a direction opposite to the normal operating polarity. Latch-up is reduced in a semiconductor layer corresponding to higher dopant concentrations, which thereby provide a layer having comparatively higher conductivity (lower resistivity). A highly resistive substrate, however, would exacerbate the latch-up phenomenon. [0007]
    [0008] High frequency communications microchips require that inductors be integrated into a microchip to achieve a required circuit performance and size, as stated earlier. If an integrated inductor were formed over the EPI layer under discussion, the inductor would induce eddy currents into the highly conductive substrate thereby incurring a large energy loss. To be energy efficient and therefore low loss, the integrated inductor would have to be formed over a highly resistive substrate. A semiconductor device, therefore, must incorporate trade-offs within its design to eliminate the generation of spurious currents and successfully accommodate integrated inductors. However, achievement of the required trade-offs currently requires many additional process steps in the construction of the semiconductor device thereby adding substantial manufacturing time and therefore cost to the semiconductor wafer. [0008]
    [0009] Accordingly, what is needed in the art is a simplified and more cost-effective way to accommodate integrated inductors into semiconductor wafers. [0009] SUMMARY OF THE INVENTION
    [0010] To address the above-discussed deficiencies of the prior art, the present invention provides for a method of manufacturing a simplified high Q inductor substrate and a semiconductor device having that substrate. In one embodiment, the method for manufacturing the simplified high Q inductor substrate comprises forming a base substrate over a semiconductor wafer, wherein the base substrate has a given dopant concentration and then forming an epitaxial (EPI) layer over the base substrate that uniquely has differently doped regions. The EPI layer includes epitaxially forming a first doped region in the EPI layer over the base substrate and then epitaxially forming a second doped region in the EPI layer over the first doped region. The first doped region preferably has a dopant concentration greater than the given dopant concentration of the base substrate, and the second doped region has a dopant concentration less than the first doped region. [0010]
    [0011] The present invention therefore introduces the broad concept of manufacturing a simplified high Q inductor substrate through the forming of the EPI layer containing at least two dopant concentrations. These differently doped regions provide a balance in the semiconductor device between maximizing the Q for an integrated inductor formed in the device and maintaining a required latch-up resistance for the device. [0011]
    [0012] Forming the base substrate, in one embodiment of the present invention, includes doping the base substrate with a p-type dopant to a dopant concentration ranging from about 10[0012] 14 cm−3 to about 1016 cm−3 wherein a dopant concentration of about 10 15 cm−3 is typical.
    [0013] In an embodiment to be illustrated and described, epitaxially forming an EPI layer includes epitaxially forming an EPI layer having first and second doped regions to a thickness ranging from about 3 μm to about 7 μm. [0013]
    [0014] Epitaxially forming a first doped region in the EPI layer, in an alternate embodiment, includes doping the first doped region with a p-type dopant to a dopant concentration equal to or greater than about 10[0014] 17 cm−3. In a further aspect of this embodiment, a dopant concentration of about 1018 cm−3 is used, and the first doped region has a thickness ranging from about 0.5 μm to about 2 μm.
    [0015] In yet another embodiment of the present invention, epitaxially forming a second doped region over the first doped region includes doping the second doped region with a p-type dopant to a dopant concentration ranging from about 10[0015] 14 cm−3 to about 1016 cm−3 wherein a dopant concentration of about 10 1 cm−3 is typical. The second doped region has a thickness ranging from about 3 μm to about 5 μm.
    [0016] In another aspect, the present invention provides a semiconductor wafer that comprises a base substrate that is formed over a semiconductor wafer and that has a given dopant concentration. An epitaxial (EPI) layer is formed over the base substrate, which includes at least first and second doped regions. The first doped region is located over the base substrate and has a dopant concentration greater than the given dopant concentration of the base substrate. The second doped region is located over the first doped region and has a dopant concentration less than the first doped region. While two doped regions have been specifically set forth, those who are skilled in the art will appreciate that other embodiments of the present invention could provide for more than two differently doped regions within the EPI layer. [0016]
    [0017] The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form. [0017] BRIEF DESCRIPTION OF THE DRAWINGS
    [0018] For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [0018]
    [0019] FIG. 1 illustrates a diagram showing a prior art construction of an integrated circuit wafer that will support a high Q inductor; [0019]
    [0020] FIG. 2 illustrates a diagram showing an embodiment of an integrated circuit wafer that will support a high Q inductor constructed according to the principles of the present invention; [0020]
    [0021] FIG. 3 illustrates a diagram showing an embodiment of an integrated circuit wafer constructed according to the principles of the present invention having a high Q thick metal inductor; and [0021]
    [0022] FIG. 4 illustrates a flow diagram of a method that may be used to construct the integrated circuit wafer of FIG. 2. [0022] DETAILED DESCRIPTION
    [0023] Referring initially to FIG. 1, illustrated is a diagram showing a prior art construction of an integrated circuit wafer [0023] 100 that will support a high Q inductor. The integrated circuit wafer 100 includes a substrate 105, an induced layer 110 and an EPI layer 115. The substrate 105 has a positive dopant with a P− dopant concentration that is typically about 10 15 cm−3 making the substrate 105 highly resistive electrically. The induced layer 110 is a thin, highly conductive layer that is constructed by diffusing or implanting a P+ dopant into the substrate 105. A P+ dopant concentration of 1018 cm−3 is typical. The EPI layer 115 is then grown on the induced layer 110 and has a P− dopant concentration of about 105 cm3.
    [0024] A typical diffusion process which may be used to form the induced layer [0024] 110 includes the following steps: 1) Brush scrub cleaning, 2) 100:1 HF cleaning, 3) Deposit solid diffusion source, 4) Deposit cap layer, 5) Drive in dopants, 6) Remove solid diffusion source, and 7) Clean wafer for EPI growth.
    [0025] A typical implantation process which may also be used to form the induced layer [0025] 110 includes the following steps: 1) Brush scrub cleaning, 2) 100:1 HF cleaning, 3) Implant dopants, 4) Drive in dopants, and 5) Clean wafer for EPI growth.
    [0026] The integrated circuit wafer [0026] 100 provides a structure that will both support a high Q integrated inductor and prevent a latch-up condition. The substrate 105 is highly resistive and therefore does not support eddy currents that would lead to energy loss and low Q inductor circuit situations. Additionally, the induced layer 110, being highly conductive, prevents latch-up from occurring. Since the induced layer 110 is thin, it will also not support sufficient eddy current activity to cause low Q inductor current situations, as well. Unfortunately, however, the process steps needed to construct the induced layer are many and therefore both time consuming and costly.
    [0027] Turning now to FIG. 2, illustrated is a diagram showing an embodiment of an integrated circuit wafer [0027] 200 that will support a high Q inductor constructed according to the principles of the present invention. The integrated circuit wafer 200 includes a base substrate 205 and an EPI layer 210 having first and second doped regions 210A, 210B, which are preferably formed by an epitaxial process.
    [0028] The present invention includes the semiconductor wafer [0028] 200 that comprises the base substrate 205 having a given dopant concentration that is formed over the semiconductor wafer 200. The EPI layer 210 is preferably expitaxially formed over the base substrate 205, which includes first and second doped regions 210A, 210B. The first doped region 210A is located over the base substrate 205 and has a dopant concentration greater than the given dopant concentration of the base substrate 205. The second doped region 210B is located over the first doped region 210A and has a dopant concentration less than the first doped region 210A.
    [0029] In one embodiment, the first doped region [0029] 210A may be formed by using 120 ppm boron source directly fed into one dopant controller and which is then mixed with trichlorosilane (TCS) and flowed at a rate of about 5 liters/minute. The EPI layer 210 is grown at a temperature of about 1150° C. The second doped region 210B may be formed by removing the 120 ppm boron source while maintaining the TCS flow at 5 liters/minute at about 1150° C.
    [0030] The present invention therefore introduces the broad concept of manufacturing a simplified high Q inductor substrate through the forming of the EPI layer [0030] 210 containing at least two dopant concentrations. These differently doped regions 210A, 210B provide a balance in the semiconductor device between maximizing the Q for an integrated inductor formed in the device and maintaining a required latch-up resistance for the device. While the two doped regions 210A, 210B have been specifically set forth in this embodiment, those who are skilled in the art will appreciate that other embodiments of the present invention could provide for more than two differently doped regions within the EPI layer 210.
    [0031] Forming the base substrate [0031] 205 in this embodiment of the present invention includes doping the base substrate 205 with a p-type dopant to a dopant concentration ranging from about 10-cm−3 to about 1016 cm−3 wherein a dopant concentration of about 1015 cm−3 is preferred. Then, the EPI layer 210 is epitaxially formed having first and second doped regions 210A, 210B to a thickness ranging from about 3 μm to about 7 μm. The first doped region 210A has a thickness ranging from about 0.5 μm to about 2 μm, and the second doped region 210B has a thickness ranging from about 3 μm to about 5 μm.
    [0032] Epitaxially forming the first doped region [0032] 210A in the EPI layer 210 includes doping the first doped region 210A with a p-type dopant to a dopant concentration equal to or greater than about 1017 cm−3 wherein a dopant concentration of about 1018 cm−3 is preferably achieved. Then epitaxially forming the second doped region 210B over the first doped region 210A includes doping the second doped region 210B with a p-type dopant to a dopant concentration ranging from about 1014 cm−3 to about 1016 cm−3 wherein a dopant concentration of about 1015 cm−3 is preferred.
    [0033] Therefore, the base substrate [0033] 205 is highly resistive electrically, the first doped region 210A of the EPI layer 210 is highly conductive and the second doped region 210B of the EPI layer 210 is highly resistive. The integrated circuit wafer 200 affords a structure that will both support a high Q integrated inductor and prevent a latch-up condition as seen in the prior art example of FIG. 1. However, epitaxially forming the EPI layer 210 using two differently doped regions allows the structure to be constructed using basically only one additional process step wherein only the dopant concentration is reduced to form the second doped region 210B. The time at which the dopant concentration is reduced, and the amount of the dopant concentration reduction determine the thickness of the first doped region 210A and the resistivity of the second doped region 210B, respectively. This process may be accomplished much more quickly, easily and cost effectively than the diffusion or the implantation processes used in the example of FIG. 1.
    [0034] Turning now to FIG. 3, illustrated is a diagram showing an embodiment of an integrated circuit wafer [0034] 300 constructed according to the principles of the present invention having a high Q thick metal inductor. The integrated circuit wafer 300 includes a base substrate 305, an EPI layer 310 having first and second doped regions 310A, 310B, first and second field effect transistors (FETs) 315, 320 having sources, drains and interposed gates, an inter-level dielectric region 325 having metal interconnections 330 and a thick metal inductor 335.
    [0035] The integrated circuit wafer [0035] 300 employs the first doped region 310A of the EPI layer 310, which is highly conductive and the second doped region 310B of the EPI layer 310, which is highly resistive to afford a structure that will both support a high Q integrated inductor and prevent a latch-up condition as seen in FIG. 2. The thick metal inductor 335 is located well “up-level” from the first and second FETs 315, 320 and is connected to other appropriate circuit components through the metal interconnections 330 in the inter-level dielectric region 325.
    [0036] Turning now to FIG. 4, illustrated is a flow diagram of a method [0036] 400 that may be used to construct the integrated circuit wafer 200 of FIG. 2. The method 400 of manufacturing a simplified high Q inductor substrate starts in a step 405 and continues in a step 410 with the forming of a base substrate over a semiconductor wafer. The base substrate formed in the step 410 has a given dopant concentration ranging from about 1014 cm−3 to about 1016 cm−3 wherein a dopant concentration of about 1015 cm−3 is typical. Then, an EPI layer is formed over the base substrate to a thickness ranging from about 3 μm to about 7 μm in steps 415A and 415B, that uniquely has differently doped regions.
    [0037] The EPI layer includes epitaxially forming a first doped region in the EPI layer in the step [0037] 415A over the base substrate and then epitaxially forming a second doped region in the EPI layer over the first doped region in the step 415B. The first doped region formed in the step 415A has a dopant concentration greater than the given dopant concentration of the base substrate formed in the step 410. The first doped region has a dopant concentration equal to or greater than about 1017 cm−3, where a dopant concentration of about 1018 cm−3 is typical. The first doped region has a thickness ranging from about 0.5 μm to about 2 μm.
    [0038] The second doped region in the EPI layer formed in the step [0038] 415B has a dopant concentration less than the first doped region. The second doped region has a dopant concentration ranging from 1014 cm −3 to about 1016 cm−3 wherein a dopant concentration of about 1015 cm−3 is typical. The second doped region has a thickness ranging from about 3 μm to about 5 μm.
    [0039] The thickness of the first doped region of the EPI layer formed in the steps [0039] 415A and 415B is determined by a first length of time that the first dopant concentration is applied. Then, the dopant concentration is reduced and the growth of the EPI layer is continued for a second length of time to determine the thickness of the second doped region. The method 400 ends in a step 420 when the second length of time is complete. The method 400 of using a single EPI layer with two separate doped regions greatly simplifies the manufacture of a structure, that will support a high Q integrated inductor while inhibiting latch-up, as compared to the current use of a diffusion or implantation process.
    [0040] Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form. [0040]
    权利要求:
    Claims (32)
    [1" id="US-20010009795-A1-CLM-00001] 1. A method for manufacturing a semiconductor substrate, comprising:
    forming a base substrate over a semiconductor wafer, the base substrate having a given dopant concentration; and
    forming an epitaxial (EPI) layer over the base substrate, including:
    epitaxially forming a first doped region in the EPI layer over the base substrate, the first doped region having a dopant concentration greater than the given dopant concentration of the base substrate; and
    epitaxially forming a second doped region in the EPI layer over the first doped region, the second doped region having a dopant concentration less than the first doped region.
    [2" id="US-20010009795-A1-CLM-00002] 2. The method as recited in
    claim 1 wherein completing formation of the semiconductor device includes forming an inductor in the semiconductor device.
    [3" id="US-20010009795-A1-CLM-00003] 3. The method as recited in
    claim 1 wherein forming a base substrate includes doping the base substrate with a p-type dopant.
    [4" id="US-20010009795-A1-CLM-00004] 4. The method as recited in
    claim 1 wherein forming a base substrate include doping the base substrate to a dopant concentration ranging from about 1014 cm−3 to about 1016 cm−3.
    [5" id="US-20010009795-A1-CLM-00005] 5. The method as recited in
    claim 4 wherein doping the base substrate includes doping the base substrate to a dopant concentration of about 1015 cm−3 with a p-type dopant.
    [6" id="US-20010009795-A1-CLM-00006] 6. The method as recited in
    claim 1 wherein epitaxially forming a first doped region in the EPI layer includes doping the first doped region with a p-type dopant.
    [7" id="US-20010009795-A1-CLM-00007] 7. The method as recited in
    claim 1 wherein epitaxially forming a first doped region in the EPI layer includes doping the first doped region to a dopant concentration equal to or greater than about 1017 cm−3.
    [8" id="US-20010009795-A1-CLM-00008] 8. The method as recited in
    claim 7 wherein doping the first doped region includes doping the first doped region to a dopant concentration of about 1018 cm−3 with a p-type dopant.
    [9" id="US-20010009795-A1-CLM-00009] 9. The method as recited in
    claim 8 wherein doping the first doped region includes using a 120 ppm boron source directly fed into one dopant controller and mixed with trichlorosilane flowed at 5 liters/minute and at a temperature of 1150° C.
    [10" id="US-20010009795-A1-CLM-00010] 10. The method as recited in
    claim 1 wherein epitaxially forming a second doped region over the first doped region includes doping the second doped region with a p-type dopant.
    [11" id="US-20010009795-A1-CLM-00011] 11. The method as recited in
    claim 1 wherein epitaxially forming a second doped region over the first doped region includes doping the second doped region to a dopant concentration ranging from about 1014 cm−3 to about 1016 cm−3.
    [12" id="US-20010009795-A1-CLM-00012] 12. The method as recited in
    claim 11 wherein doping the second doped region includes discontinuing a flow of 120 ppm boron while maintaining a trichlorosilane flow at 5 liters/minute at 1150° C.
    [13" id="US-20010009795-A1-CLM-00013] 13. The method as recited in
    claim 11 wherein doping the second doped region includes doping the second doped region to a dopant concentration of about 1015 cm−3 with a p-type dopant.
    [14" id="US-20010009795-A1-CLM-00014] 14. The method as recited in
    claim 1 wherein epitaxially 2 forming an EPI layer includes epitaxially forming an EPI layer to a thickness ranging from about 3 μm to about 7 μm.
    [15" id="US-20010009795-A1-CLM-00015] 15. The method as recited in
    claim 1 wherein epitaxially forming a first doped region in the EPI layer includes epitaxially forming a first doped region to a thickness ranging from about 0.5 μm to about 2 μm.
    [16" id="US-20010009795-A1-CLM-00016] 16. The method as recited in
    claim 1 wherein epitaxially forming a second doped region over the first doped region includes forming a second doped region to a thickness ranging from about 3 μm to about 5 μm.
    [17" id="US-20010009795-A1-CLM-00017] 17. The method as recited in
    claim 1 wherein forming a base substrate includes forming a p-type substrate to a dopant concentration of about 1015 cm−3, epitaxially forming a first doped region over the base substrate includes epitaxially forming a p-type first region to a dopant concentration of about 1018 cm−3, and forming a second doped region over the first doped region includes epitaxially forming a p-type first region to a dopant concentration of about 1015 cm−3.
    [18" id="US-20010009795-A1-CLM-00018] 18. A semiconductor wafer, comprising:
    a base substrate over a semiconductor wafer, the base substrate having a given dopant concentration;
    an epitaxial (EPI) layer over the base substrate, including:
    an epitaxially formed first doped region located over the base substrate, the first doped region having a dopant concentration greater than the given dopant concentration of the base substrate; and
    an epitaxially formed second doped region located over the first doped region, the second doped region having a dopant concentration less than the first doped region.
    [19" id="US-20010009795-A1-CLM-00019] 19. The semiconductor wafer as recited in
    claim 18 further comprising an integrated circuit having an inductor incorporated therein.
    [20" id="US-20010009795-A1-CLM-00020] 20. The semiconductor wafer as recited in
    claim 18 wherein the base substrate has a p-type dopant.
    [21" id="US-20010009795-A1-CLM-00021] 21. The semiconductor wafer as recited in
    claim 18 wherein the base substrate is doped to a concentration ranging from about 1014 cm−3 to about 1016 cm−3.
    [22" id="US-20010009795-A1-CLM-00022] 22. The semiconductor wafer as recited in
    claim 21 wherein the base substrate is doped to a concentration of about 1015 cm−3 with a p-type dopant.
    [23" id="US-20010009795-A1-CLM-00023] 23. The semiconductor wafer as recited in
    claim 18 wherein the epitaxially formed first doped region is doped with a p-type dopant.
    [24" id="US-20010009795-A1-CLM-00024] 24. The semiconductor wafer as recited in
    claim 18 wherein the epitaxially formed first doped region is doped to a concentration equal to or greater than about 1017 cm−3.
    [25" id="US-20010009795-A1-CLM-00025] 25. The semiconductor wafer as recited in
    claim 23 wherein the first doped region is doped to a concentration of about 1018 cm−3 with a p-type dopant.
    [26" id="US-20010009795-A1-CLM-00026] 26. The semiconductor wafer as recited in
    claim 18 wherein the epitaxially formed second doped region is doped with a p-type dopant.
    [27" id="US-20010009795-A1-CLM-00027] 27. The semiconductor wafer as recited in
    claim 18 wherein the epitaxially formed second doped region is doped to a concentration ranging from about 1014 cm−3 to about 1016 cm−3.
    [28" id="US-20010009795-A1-CLM-00028] 28. The semiconductor wafer as recited in
    claim 27 wherein the second doped region is doped to a concentration of about 1015 cm−3 with a p-type dopant.
    [29" id="US-20010009795-A1-CLM-00029] 29. The semiconductor wafer as recited in
    claim 18 wherein the epitaxially formed EPI layer has a thickness ranging from about 3 μm to about 7 μm.
    [30" id="US-20010009795-A1-CLM-00030] 30. The semiconductor wafer as recited in
    claim 18 wherein the epitaxially formed first doped region has a thickness ranging from about 0.5 μm to about 2 μm.
    [31" id="US-20010009795-A1-CLM-00031] 31. The semiconductor wafer as recited in
    claim 18 wherein the epitaxially formed second doped region has a thickness ranging from about 3 μm to about 5 μm.
    [32" id="US-20010009795-A1-CLM-00032] 32. The semiconductor wafer as recited in
    claim 18 wherein the epitaxially formed first doped region provides a Q equal to or greater than about 10.
    类似技术:
    公开号 | 公开日 | 专利标题
    US6410974B2|2002-06-25|Simplified high Q inductor substrate
    US7220654B2|2007-05-22|Method for manufacturing semiconductor substrate
    DE60036410T2|2008-05-29|METHODS FOR GENERATING A FIELD EFFECT TRANSISTOR STRUCTURE WITH PARTIALLY ISOLATED SOURCE / DRAIN TRANSITIONS
    US5897363A|1999-04-27|Shallow junction formation using multiple implant sources
    US6365447B1|2002-04-02|High-voltage complementary bipolar and BiCMOS technology using double expitaxial growth
    US6265248B1|2001-07-24|Method for producing semiconductor-on-insulator structure with reduced parasitic capacitance
    US20070158741A1|2007-07-12|LDMOS Device and Method of Fabrication of LDMOS Device
    US7579670B2|2009-08-25|Integrated filter having ground plane structure
    KR20190003287A|2019-01-09|High voltage resistor device
    EP0183623A2|1986-06-04|Precision high-value MOS capacitors
    US6528382B2|2003-03-04|Semiconductor device and method for fabricating the same
    US6225182B1|2001-05-01|Simplified high Q inductor substrate
    US7466212B2|2008-12-16|Semiconductor filter structure and method of manufacture
    WO1990016081A1|1990-12-27|HIGH DENSITY BiCMOS CIRCUITS AND METHODS OF MAKING SAME
    US6707116B2|2004-03-16|Integrated circuit and manufacturing method therefor
    JPH0521448A|1993-01-29|Manufacture of semiconductor device
    US6395611B1|2002-05-28|Inductor or low loss interconnect and a method of manufacturing an inductor or low loss interconnect in an integrated circuit
    US6677208B2|2004-01-13|Transistor with bottomwall/sidewall junction capacitance reduction region and method
    US6445058B1|2002-09-03|Bipolar junction transistor incorporating integral field plate
    EP1743378A1|2007-01-17|Semiconductor device and method of manufacturing such a device
    JPH06112217A|1994-04-22|Semiconductor device and its manufacture
    US6437421B1|2002-08-20|Self-aligned dual-base semiconductor process and structure incorporating multiple bipolar device types
    JP2001274395A|2001-10-05|Semiconductor device and manufacturing method thereof
    US20030113980A1|2003-06-19|Method for manufacturing and structure of semiconductor assembly with a shallow trench device region
    EP0774167A1|1997-05-21|A power semiconductor device
    同族专利:
    公开号 | 公开日
    EP0999580A3|2003-06-04|
    DE69936175D1|2007-07-12|
    EP0999579A3|2003-06-04|
    EP0999580B1|2008-01-02|
    DE69936175T2|2008-01-24|
    TW550654B|2003-09-01|
    DE69937868T2|2009-01-02|
    US6410974B2|2002-06-25|
    JP2000150783A|2000-05-30|
    EP0999579A2|2000-05-10|
    EP0999580A2|2000-05-10|
    KR20000035195A|2000-06-26|
    EP0999579B1|2007-05-30|
    SG87846A1|2002-04-16|
    SG91840A1|2002-10-15|
    DE69937868D1|2008-02-14|
    TW437085B|2001-05-28|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US7227222B2|2001-01-16|2007-06-05|Sony Corporation|Semiconductor device and manufacturing method thereof|
    US8836063B2|2011-05-04|2014-09-16|Micronas Gmbh|Integrated passive component|US3878001A|1970-07-13|1975-04-15|Siemens Ag|Method of making a hypersensitive semiconductor tuning diode|
    US4224631A|1978-10-25|1980-09-23|Raytheon Company|Semiconductor voltage reference device|
    US4458158A|1979-03-12|1984-07-03|Sprague Electric Company|IC Including small signal and power devices|
    GB2163002B|1984-08-08|1989-01-05|Japan Res Dev Corp|Tunnel injection static induction transistor and its integrated circuit|
    JPS6272144A|1985-09-25|1987-04-02|Toshiba Corp|Semiconductor device|
    IT1215024B|1986-10-01|1990-01-31|Sgs Microelettronica Spa|PROCESS FOR THE FORMATION OF A HIGH VOLTAGE SEMICONDUCTOR MONOLITHIC DEVICE|
    KR940004847A|1992-08-04|1994-03-16|리차드 제이. 컬|A method of forming an epitaxial double diffusion metal oxide transistor structure having a low threshold hold voltage|
    DE69434937D1|1994-06-23|2007-04-19|St Microelectronics Srl|Process for the production of power components in MOS technology|
    GB2301706A|1995-06-01|1996-12-11|Plessey Semiconductors Ltd|Intergrated inductor arrangement|
    US5712501A|1995-10-10|1998-01-27|Motorola, Inc.|Graded-channel semiconductor device|
    JP4061418B2|1996-07-30|2008-03-19|株式会社Ｓｕｍｃｏ|Silicon substrate and manufacturing method thereof|
    US5805043A|1996-10-02|1998-09-08|Itt Industries, Inc.|High Q compact inductors for monolithic integrated circuit applications|
    US5831331A|1996-11-22|1998-11-03|Philips Electronics North America Corporation|Self-shielding inductor for multi-layer semiconductor integrated circuits|
    US5734194A|1997-01-31|1998-03-31|Motorola, Inc.|Semiconductor device and method of making|
    US6093951A|1997-06-30|2000-07-25|Sun Microsystems, Inc.|MOS devices with retrograde pocket regions|
    AT362199T|1997-12-22|2007-06-15|Ihp Gmbh|METHOD FOR PRODUCING A SEMICONDUCTOR SUBSTRATE WITH A LOWERED INSULATION LAYER FOR INTEGRATED CIRCUITS|
    US6169008B1|1998-05-16|2001-01-02|Winbond Electronics Corp.|High Q inductor and its forming method|
    US6020611A|1998-06-10|2000-02-01|Motorola, Inc.|Semiconductor component and method of manufacture|
    US6064088A|1998-06-15|2000-05-16|Xemod, Inc.|RF power MOSFET device with extended linear region of transconductance characteristic at low drain current|
    US5918121A|1998-07-09|1999-06-29|Winbond Electronics Corp.|Method of reducing substrate losses in inductor|US8421158B2|1998-12-21|2013-04-16|Megica Corporation|Chip structure with a passive device and method for forming the same|
    US8384189B2|2005-03-29|2013-02-26|Megica Corporation|High performance system-on-chip using post passivation process|
    US8178435B2|1998-12-21|2012-05-15|Megica Corporation|High performance system-on-chip inductor using post passivation process|
    US6303423B1|1998-12-21|2001-10-16|Megic Corporation|Method for forming high performance system-on-chip using post passivation process|
    JP4969715B2|2000-06-06|2012-07-04|ルネサスエレクトロニクス株式会社|Semiconductor device|
    US6759275B1|2001-09-04|2004-07-06|Megic Corporation|Method for making high-performance RF integrated circuits|
    JP3898024B2|2001-10-19|2007-03-28|Ｎｅｃエレクトロニクス株式会社|Integrated circuit and manufacturing method thereof|
    US8021976B2|2002-10-15|2011-09-20|Megica Corporation|Method of wire bonding over active area of a semiconductor circuit|
    CN1901161B|2005-07-22|2010-10-27|米辑电子股份有限公司|Method for fabricating a circuitry component by continuous electroplating and circuitry component structure|
    US8749021B2|2006-12-26|2014-06-10|Megit Acquisition Corp.|Voltage regulator integrated with semiconductor chip|
    KR101332228B1|2008-12-26|2013-11-25|메키트 에퀴지션 코포레이션|Chip packages with power management integrated circuits and related techniques|
    DE102011016159B3|2011-04-05|2012-10-18|Micronas Gmbh|Arrangement of an integrated passive component and a semiconductor body arranged on a metal carrier|
    DE102011100487A1|2011-05-04|2012-11-08|Micronas Gmbh|Integrated passive component|
    法律状态:
    2002-06-06| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2005-12-16| FPAY| Fee payment|Year of fee payment: 4 |
    2009-12-21| FPAY| Fee payment|Year of fee payment: 8 |
    2013-11-27| FPAY| Fee payment|Year of fee payment: 12 |
    2014-05-08| AS| Assignment|Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031 Effective date: 20140506 |
    2015-02-20| AS| Assignment|Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AGERE SYSTEMS LLC;REEL/FRAME:035059/0001 Effective date: 20140804 Owner name: AGERE SYSTEMS INC., PENNSYLVANIA Free format text: MERGER;ASSIGNOR:AGERE SYSTEMS GUARDIAN CORP.;REEL/FRAME:035058/0884 Effective date: 20020822 Owner name: AGERE SYSTEMS LLC, PENNSYLVANIA Free format text: MERGER;ASSIGNOR:AGERE SYSTEMS INC.;REEL/FRAME:035058/0895 Effective date: 20120724 |
    2016-02-02| AS| Assignment|Owner name: LSI CORPORATION, CALIFORNIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039 Effective date: 20160201 Owner name: AGERE SYSTEMS LLC, PENNSYLVANIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039 Effective date: 20160201 |
    2016-02-11| AS| Assignment|Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH CAROLINA Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 |
    2017-02-03| AS| Assignment|Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 |
    2017-11-09| AS| Assignment|Owner name: AGERE SYSTEMS GUARDIAN CORP., PENNSYLVANIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LUCENT TECHNOLOGIES, INC.;REEL/FRAME:044722/0736 Effective date: 20010130 |
    2017-12-17| AS| Assignment|Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;BROADCOM CORPORATION;REEL/FRAME:044886/0608 Effective date: 20171208 |
    2018-02-01| AS| Assignment|Owner name: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERA Free format text: SECURITY INTEREST;ASSIGNORS:HILCO PATENT ACQUISITION 56, LLC;BELL SEMICONDUCTOR, LLC;BELL NORTHERN RESEARCH, LLC;REEL/FRAME:045216/0020 Effective date: 20180124 |
    优先权:
    申请号 | 申请日 | 专利标题
    US10694598P| true| 1998-11-04|1998-11-04||
    US12447899P| true| 1999-03-15|1999-03-15||
    US09/386,132|US6225182B1|1999-08-30|1999-08-30|Simplified high Q inductor substrate|
    US09/800,049|US6410974B2|1998-11-04|2001-03-05|Simplified high Q inductor substrate|US09/800,049| US6410974B2|1998-11-04|2001-03-05|Simplified high Q inductor substrate|
    [返回顶部]